DESIGN of HIGH SPEED, LOW AREA, CARRY FLOW BCD ADDER in QCA
نویسندگان
چکیده
We can overcome the CMOS scaling problems with emerging Nanotechnology. In Nanotechnology the basic building block of digital design is QCA. The problem in design of decimal adders on Quantum dot cellular automata with reduction of QCA primitives is very limited. In this paper we present a BCD adder with less number of QCA primitives and it is compared with existing BCD adder designs. Our proposed 4-bit QCA-BCD adder results yield increase in speed 66% and reduction in area approximately and 93% respectively compared to the best existing design [1].
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